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# Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling

### Abstract

* PCM:
  * memory technology that can increase main memory capacity in a cost-effective and power-efficient manner 
  * endure only 10^7 - 10^8 writes, lifetime short. Non-uniformity in writes reduces the available lifetime. 
* Wear-Leveling: can make writes to PCM cells uniform, but require large storage tables and indirection, thus latency overheads 
* Propose: Start-Gap, which is a simple, novel, and effective wear-leveling technique that uses only two registers 
  * Extend lifetime
  * Simple extension: more robust 

### Introduction 

* PCM: 
  * 2x-4x slower than DRAM, can provide up to 4x more density than DRAM 
  * Limited number of writes to each cell 
  * Non-uniformity causes the actual lifetime to be 20x lower than lifetime achievable under ideal conditions 
* Wear leveling
  * Makes the writes uniform by remapping heavily written lines to less frequently write lines 
  * Track write counts associated with each line and an indirection table to perform address mapping to achieve uniform wear-out of the system 
  * Hardware required scales with RAM that is needed, look up adds latency and increase power consumption, additional design, verification, and testing cost 
* Goal: simple, effective wear-leveling mechanism that obviates the overheads above and achieve similar lifetime close to perfect wear-leveling 
* Insight: algebraic mapping between logical and physical address 
* Idea 
  * Start-Gap: 
    * Gap: keeps track of how many lines have moved 
    * When all lines have moved, the Start register is incremented to keep track of the number of times all lines have moved 
    * mapping from logical to physical: simple arithmetic operation of Gap and Start registers with the logical address 
  * Security threat: extend to tolerate such attacks by dividing the memory into few regions and managing each region independently 

### Background and Motivation 

* PCM
  * Limited write endurance 
  * Suffer from non-uniformity 
* Table-based wear-leveling methods require 
  * Significant hardware overhead 
  * Suffer from increased latency 
* Goal: avoid storage and latency overheads of existing wear-leveling algorithms, and achieve lifetime close to perfect wear-leveling 

### Experimental Methodology 

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5IS34fXE4xRx5cfD6%2Fimage.png?alt=media\&token=861dffcb-c25f-4dc9-84d7-2b194db50696)

![Normalized Endurance (NE), close to 100%: achieve system lifetime similar to max possible lifetime](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5J2GEISN9sLh_DnO8%2Fimage.png?alt=media\&token=4dc3ae41-9218-4f46-a975-b533685346ca)

### Start-Gap Wear Leveling

* Key insight: use algebraic mapping between logical and physical addresses, and avoids tracking per-line write counts 
* Performs wear leveling by periodically moving each line to its neighboring location, regardless of the write traffic to the line
* Two registers: Start, Gap
  * Gap: number of lines relocated in memory 
  * Start: how many times all the lines in memory have been relocated 
* Extra memory line (GapLine): facilitate data movement 

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5JbZ1hfpdAJqQL--C%2Fimage.png?alt=media\&token=425f1cb4-e28d-41f2-b041-a6f0abce7ea0)

* Gap is moved by 1 location once every psi writes to memory: copying the content of location gap - 1 to GapLine and decrementing the Gap register (Figure 5(b))
* After 8 movements, all the lines from 8-15 get shifted by 1 (Figure 5(c))
* Figure 5(e): contents of all lines have shifted by exactly 1 location, and hence the Start register is incremented by 1 

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5LvedwCiWBeWHGKcT%2Fimage.png?alt=media\&token=5ad62221-0a58-4699-8ae3-7dcc615fc2b8)

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5LxP2g1Fkk7C8dcUt%2Fimage.png?alt=media\&token=66e1523f-3212-4706-b0ce-3f242958a0c1)

* Overhead controlled by psi (gap write interval) 

### Address-Space Randomization 

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5MkhouUGwaW9RkACU%2Fimage.png?alt=media\&token=11de3375-8b0e-4350-a234-73290b37dbfc)

* The randomizer provides a (pseudo) random mapping of a given Logical Address (LA) to an Intermediate Address (IA)
* Due to random assignment of LA to IA, all regions are likely to get a total write traffic very close to the average, and the spatial correlation of heavily written lines among LA is unlikely to be present among IA.

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5NERhnyfyrlUdFAOn%2Fimage.png?alt=media\&token=b239e4ca-03ef-4a19-abe7-8973f57ae685)

![](https://2097630930-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MVORxAomcgtzVVUqmws%2F-Mk53qLNzrg3lqxQi-ur%2F-Mk5NKdUll4xNsF8gEIH%2Fimage.png?alt=media\&token=dc706ddb-5334-49db-b795-07598200eeac)

### Wear leveling under adversarial settings

* An adversary who knows about the wear leveling technique can design an attack that stresses a few lines in memory and cause the system to reach the endurance limit, and fail 
* Solution:
  * Region Based Start-Gap (RBSG) 
    * divides the memory into several regions and manages each region independently using a separate Start and Gap
    * If a region is written heavily it will now undergo Gap Movement faster than other regions, preventing line failure from repeated writes
  * Another orthogonal approach to tolerate attacks is to increase the time to write to the same line (Delayed Write Policy with a Delay Write Factor (DWF))